Pipelining is one technique used to make processors operate faster. Pipelining entails separating instruction and/or data paths into a number of stages. Pipelining enables data in different pipe stages to be operated on simultaneously.
A data path may be pipelined by adding a set of registers between each pair of pipe stages. Computational logic in the stage may operate on data in an adjacent register. Pipelining the data path may increase the speed at which results exit of the data path. Costs associated with pipelining include increased area for the registers and added latency corresponding to the number of clock cycles needed to initially fill (or prime) the pipeline, e.g., n clock stages in a pipeline with n stages. However, once the pipeline is filled, results may be issued nearly every clock cycle.
In certain pipelined data paths the number of cycles needed to process data in the stage may vary between stages, i.e., asynchronously. To prevent data from a stage from being written over valid data still being processed in the next stage, many processors including asynchronous pipelined data paths implement a handshake protocol between stages. In order for data to be moved up the pipe from one stage to the next stage, the two stages must agree that both are ready for the transfer. However, such handshake protocols require at least a clock cycle to complete, which introduces additional latency to the system.